LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
--USE ieee.std_logic_arith.all;
--USE ieee.std_logic_unsigned.ALL;

ENTITY counter IS
	PORT ( 	clk: IN STD_LOGIC;
			reset: IN STD_LOGIC;
			y: OUT INTEGER);
END counter ;

ARCHITECTURE counter OF counter IS
BEGIN
	counter: PROCESS (clk,reset)
		VARIABLE c: INTEGER:=0;
	BEGIN	
		--increment the counter
		if (clk'event and clk = '1') then
			c := c+1;
			-- reset the counter
			if reset = '1' then
				y <= c;
				c := 0;
			end if;
		end if;
		
	END PROCESS;
		
END counter ;
